In Internet network infrastructure data transport using TCP/IP or RTP is implemented at layers 2 & 1 with egress packet conversion and VCSELs. Packet processors for ingress (“header shreaders”) manage flow control for QoS (and provide a good place to foil net neutrality).

There are no “buses” between Internet routers – just optical fiber carrying wavelenth-dense multiplexing at bandwidths exceeding 1Tbps. The same trend will come to dominate in chip-to-chip communications.

The IC industry has embraced the OSI model used select chip to chip data classes. For example: PCIexpress, originally created to move data between the CPU and the GPU, has evolved with Gen3 to become a standard mass storage interface. For mobile applications, JEDEC UFS provides an interface to NAND Flash storage. And the new MIPI LLI standard provides low latency, low power, chip-to-chip interfaces.

This is a death knell for high pin count packages. Using buses to achieve bandwidth between ICs in a system will evolve to specialized high-speed Ser/Des IO.

Specialized IP that interfaces to internal standard SoC buses, like AXI, AHB, OCP, etc. will packetize, serialize/deserialize, and de-packetize data using increasingly higher transport speeds while reducing IC power and area. Ultimately this function will be virtually absorbed into the I/O pad. The reduction in pin count will simplify package and PCB routing and signal integrity, yield higher system performance and low cost.

What is MIPI LLI

The primary objective of LLI is to provide low latency interface for internal or external devices (e.g. DRAM) between two ICs. The bandwidth is scalable from 2.9 Gb/sec over one differential signal pair, called a lane, to 17 Gb/sec over 6 lanes – in each direction. Differential serial data is driven and received by Type 1 M-PHY’s defined by the PHY working group of the MIPI Alliance. Each data lane has an M-PHY at both ends. The analog PHY’s are managed by an LLI controller on their respective ICs, and those controllers interface to the rest of the IC.
LLI ensures Quality of Service for data transfers between the two chips. Critical data transfers between the devices of the two chips are allocated higher priority as members of the Low Latency traffic class. There is a critical need that must be filled for QoS requirements, and that is to minimize data loss. To this end, the LLI controller is a layered structure that conforms to the familiar OSI model.
When behaving as a transmitter, the LLI controller, regardless of whether it resides on the system master or slave, grabs the transactions from the local interconnect into the Interconnect Adaptation Layer, frames it as command or data frames in the Transaction Layer, and adds a channel ID and implements a credit based flow control protocol in the Data Link Layer. The frames are now passed to the PHY Adapter layer that adds a frame sequence number and CRC checksum, optionally encodes the complete frame to a set of 10 bit symbols, and distributes those symbols to the available or active M-PHY’s. The M-PHY’s transmit to their counterparts on the other chip as a pair of differential signals.
On the receiver side, the reverse happens. The M-PHY and LLI combination convert the 10 bit symbols to bytes, using the channel ID’s to reassemble them into frames, which are then sent up the LLI stack for proper handling, like error detection and correction, contention detection and recovery, and generating back pressure to implement flow control. All error handling is managed between the two sets of LLI controllers and M-PHY’s.
A device on an interconnect may initiate a transaction or respond to a request or both. It may be serviced by either a low latency or best effort traffic class, or both, depending on the nature of the transaction. For these reasons, the LLI controller, which is another device on the interconnect, should be able to handle any and all of these scenarios.

The Prime Solution

The Website Conversion Funnel

Historically this happens by demonstrating your products or services at trade shows or through direct sales contacts. While effective the “cost per lead” can be several hundred dollars. Leads generated through a website can be an order of magnitude less – if you know how.
The process can be viewed a funnel.

• Awareness – Can engineers find your website?
• Interest – Do they explore or bounce?
• Desire – Do you “educate” them adequately to take the next step?
• Action – Do you convert them into a lead for the sales team?

The AIDA acronym is ~100 years old but still relevant

KPI

If you are not tracking and analyzing visitor traffic your website is as effective as a yellow page ad. What are the Key Performance Indicators (KPI) for your business: Cost of Sales, Cost of Goods, Gross Profit Margin? Define an analogous set of KPI for your website. Unique visitors, page views, length of visit, conversion via lead forms, and Cost per lead. Consider all of your acquisition costs in detail – how much do you spend on press releases, events, affiliate marketing, advertising, etc. Measure the CPL and aggregate CPL against the sales opportunities acquired from your website.

The right links, the right keywords

Engineers find potential solutions through search and links on authoritative web sites (online journals and domain-specific news sites). A keyword isn’t a “word”, it’s the word and/or phrase that people use to find solutions. What does your target customer-engineer search for? You can utilize Google Webmaster tools to determine which keywords were used by the visitors to your site and the inbound links. You will need other tools to understand how the keywords that describe your products and services rank against competitors. And your search competitors include companies that may not compete with your products, but use similar words for their products. The key to securing greater investment for the purpose of SEO is in knowing the value of every visitor that arrives from an organic search. [website magazine].

SERPs

Search Engine Rank Pages or “Serp” tells you where your keyword ranks on various search engines. Google (with ~80% of the search market) is the obvious one to start with. If the keywords for your solution don’t occur on page one (the top 10) you won’t get found. By the way, you can’t determine this by simply searching on Google. Google (and others) filter the results, i.e. what you searched for yesterday affects the results you get today. Your cookies and your IP address provide Google with a trail of information to bias your search results. Google Adwords provides keyword analysis and a number of SEO services can help you determine your best keywords and their ranking.

Advertising

If your keywords don’t rank high, you can buy your way to the top with Google Adwords. There are several reasons why this is a good tactic.

• Paid search Ads typically appear on the right side of the search page. But if there is little competition and your ads have a good quality score, Google will place them in the center (main) area with the organic (free) results.
• I assert that a paid search Ad at the top and an organic search link in the middle is better than either by itself.
• Most small-cap high technology companies (under $100M in revenue) don’t advertise with Google. There are several reasons why. Someone at the company tried it and basically poured money down the drain. Adwords does have a learning curve. If your B2E site isn’t focused on KPI you have no way of measuring the value of Adwords. I recommend spending 1% to 5% of your marketing budget on Adwords campaigns to complement organic search. If you don’t have the in-house skill, outsource or crowdsource it.
• Does Google search favor Google customers? Recent research says Yes

Landing Page Optimization

Research has shown that people make a decision to stay or leave (bounce) a website in 50mS. A couple of eye blinks. If your site is confusing, and a customer-engineer flips his “I don’t need this” bit, you’ve lost a potential customer.

• Simplify Design and Reduce Text – every pixel is either signal or noise
• Have a Clear Call to Action – Register to access restricted information, download whitepapers, etc.
• Use Images Judiciously – If you have customer testimonials, use a portrait image
• Video can be very compelling but keep them short (under two minutes). The simplest hosting solution is to create a business page on YouTube.
• ABT – Always be Testing

What you think people see on your website may not be what they see. A visitor’s background, knowledge or expectations will influence how they perceive your page. The solution is to test changes. The best approach is A/B testing, whereby some percentage of visitors see landing page “A” and some percentage see “B”. Your analytics determine which page wins. Repeat constantly.

Business Intelligence

Content is king and SEO marketers are a dime a dozen. Talk to someone who understands technology, online media channels and the steps to establishing business intelligence for your B2E company.

NAND Flash is used to replace (HDD) hard disk drives, provide cache for HDD, or extend the size of main (DRAM) memory.  End applications extend from consumer to the enterprise in segments such as:

• Consumer tablet and ultrabook computing
• Cache storage in transaction processing centers (– e.g. banking, payroll, etc.)
• I/O performance in virtualized server farms
• Secure backup for failsafe applications
• Optimizing footprint (power and space of HDD vs. SDD based on IOPS)

The controller and interface requirements for these cover a wide range of technologies. In the case of DRAM backup in server failsafe applications for instant wake up and emergency power-down protection, sophisticated wear leveling is not required.  For mass storage requirements, wear leveling and error correction codes (ECC) are critical for data integrity. The latest generation of high density multilevel cell (MLC) NAND Flash achieve up to 128Gbit in a single IC using 20nm process technology.[1]  The tradeoff for achieve high density with MLC is lower program/erase cycles and higher bit error rates, necessitating complicated cyclic codes such as Reed-Solomon (R/S) or Bose-Chaudhuri-Hocquenghem (BCH) to increase the correction capability.

Most suppliers of NAND Flash memory have adopted the ONFI (Open NAND Flash Interface) standard, which defines package pin out, signaling and interface requirements.  The latest ONFI standard is 3.0 released in March 2011.   ONFI 3.0 provides NVDDR 2.0 (also termed toggle 2) which provides up to 400M transfers per sec. This is a three-fold increase over DDR 1 (133MTps) and a ten-fold increase over SDR (40MTps).  Toggle 2 utilizes a “clock-less” mode whereby transfers are “toggled” by the data strobe (DQS).  The high data rate is supported with on-die termination and 1.8V I/O signal levels.  ONFI 3.0 also defines a reduced chip enable protocol to simplify SSD controller design.

Arasan Chip Systems provides a full ONFI 3.0 compliant NAND Flash Phy and control logic suitable for ARM based controllers in applications ranging from consumer tablets, ultrabooks and enterprise server SSD. ONFI 3.0 is backward compatible to all previous ONFI standards supporting SLC and MLC NAND Flash. A typical SSD has an ARM based NAND controller talking to many NAND flash via ONFI interface.   And, the other side of this NAND controller is plugged into the PCIe bus or SATA bus to communicate with the host CPU.  The signal flow goes from an Intel CPU to PCIe bus on the mother board to PCIe receiver on the SSD drive connected to an ARM based NAND controller interfacing to ONFI NAND controller and a set of NAND Flash ICs. Arasan’s patent-pending BCH ECC implementation uses an inversionless Berlekamp-Massey algorithm and a parallel Chien search algorithm. Up to 64b or more of error correction is provided.

• High capacity
• Low cost
• Low power
• High bandwidth

The Flash storage industry has provided capacity to support large multimedia files such as video, music and photos. Accompanying the technology improvements have been standards developments that allow multi-tasking of applications and faster web browsing. The JEDEC eMMC standard evolved from 4.1 to the current 4.5 revision. The standards also have allowed applications to migrate from parallel bus interface to serial differential transmission for higher throughput.

A separate industry consortia, the Mobile Industry Processor Interface (MIPI), is developing a high-performance, serial I/O standard for data transfers between portable embedded devices such as display, cameras and application co-processors. As performance for both specifications improved both standards it became clear that there was need for only one. In 2010, both and MIPI and JEDEC adopted the UFS as the common data transfer protocol for mobile systems.

Universal Flash Storage (UFS) Standard

The UFS standard is designed to offer a fast, reliable and simple means of supporting storage requirements in portable applications such as smart phones. UFS represents the next generation in Flash storage standards. It supports both embedded and removable card applications.

The standard features low power consumption improving battery life through efficient and smart power management and reduced component count. UFS performance varies according to the Gear or version. The current UFS Gear 1 offers 1.5Gbps while Gear 2 will have 3Gbps, and Gear 3 will handle up to 6Gbps.

The standard offers power/performance tradeoffs in the form of different power states of the M-PHY. When the device is not being used in data transfers it shifts its state among seven possible states. Each state uses less power according to the number states traversed to get to the higher power consuming data transfer state. UFS uses a 50 MHz clock and differential signaling for its serial transfers of up to four lanes. It supports both Pulse Width Modulation (PWM) and Non-Return to Zero (NRZ) data encoding.

Live Webinar

Register to Join a live Webinar on UFS presented by Arasan Chip Systems on Feb 28 6PM PST or Feb 29 10AM PST

The SMU intern program added a year to your graduation in exchange for multiple semester/summer internships. In my first internship, I designated most of the bike lanes for the City of Dallas – interesting but irrelevant to my studies. My next two internships were at Collins Radio (before it became Rockwell Collins, before it became Alcatel).

Solving for currents and voltages with R/L/C components with paper and pencil was painful, and with active components it became ridiculous. But SPICE and a card-deck changed everything. If you don’t know what a card-deck means, see this post.

Skip forward another semester and I was measuring S Parameters for 2N2222A transistors used in baseband circuits for the X.25 microwave systems that Collins was famous for.

One of the engineers I helped had spent several months in Australia working on an installation. While he was there he built an airplane, disassembled it and shipped it back in a container with company radio equipment. At that company and probably others at that time, engineers punched a time-clock, expenses and travel were scrutinized. He thought it was hysterical that the company paid to ship his airplane, and told the story often. His other hobby was playing with some magical stuff coming out of Texas Instruments – digital logic like J/K Flip-Flops and NAND gates. Several years later I ended up in a division under a VP who had co-developed 74STTL. My department head and I were pitching him on a new methodology to drastically reduce IC design time for a small decrease in area efficiency (i.e. ASIC design). He looked at a chip layout I created and told us there was no f’ing way TI would waste that much Silicon. Afterwards my boss told me to “do it anyway, just don’t let him find out”. But he did find out, when Wally Rhines took over a restructured division for Application-Specific Integrated Circuits products, services and software.